1. Field of the Invention
The present invention relates to a method of fabricating an SRAM device, by which a junction node area is stably secured in an 1T type SRAM device.
2. Discussion of the Related Art
Lately, the 1T type SRAM (static random access memory) device configured with one capacitor and one transistor has been proposed to meet the demand for high integration and performance enhancement of an SRAM device. One of the conditions for stable implementation of the 1T type SRAM device is to stably secure an electrical characteristic of an area between a transistor and a capacitor, i.e., a junction node.
FIGS. 1A to 1C are cross-sectional diagrams for explaining a method of fabricating an SRAM device according to a related art.
Referring to FIG. 1A, a device isolation layer 102 is formed on a semiconductor substrate 101 to define an active area. In doing so, the active area is divided into a cell area and a periphery area.
An oxide layer and a conductor layer are sequentially stacked on the substrate 101. And, the conductor and oxide layers are selectively patterned. Hence, a gate insulating layer 103a, a gate electrode pattern 104a, a dielectric layer 103b of a capacitor, and an upper electrode pattern 104 of the capacitor are formed in the cell area, while a gate insulating layer 103c and a gate electrode pattern 104c are formed in the periphery area.
Subsequently, LDD ion implantation is carried out on the substrate 201 to form lightly doped regions n31  in the active areas to be aligned with the gate electrode patterns, respectively.
Referring to FIG. 1B, a first insulating layer 105 and a second insulating layer 106 are sequentially stacked on the substrate 201 including the gate electrode patterns and the upper electrode pattern. In doing so, a total thickness of the first and second insulating layers 105 and 106 is about 1,000 Å.
Referring to FIG. 1C, the second and first insulating layers 106 and 105 are anisotropically etched to form spacers on sidewalls of the gate electrode patterns and the upper electrode pattern, respectively in the cell and periphery areas.
Subsequently, source/drain ion implantation is carried out on the substrate 101 to form heavily doped regions n+ in the active areas of the substrate 101 to be aligned with the spacers, respectively.
However, in the cell area of the related art 1T type SRAM device, a gap between the spacers on the sidewalls of the gate electrode and the upper electrode is so narrow that an interval, i.e., a conjunction node, between the source/drain regions cannot be sufficiently provided.
If a width of the junction node is tight, capacitance of the capacitor is lowered. In such a manner, if the capacitor performance is lowered, device reliability and throughput are degraded.